The present invention relates to a semiconductor integrated circuit and a testing method for the same, and also relates to increasing the reliability of test results.
In recent years, rapid progress in miniaturization technologies in the semiconductor manufacturing process has lead to sudden advances in providing large scale and complex semiconductor integrated circuits. As a result, semiconductor integrated circuits have become even more difficult to test. In response this problem, design methods using a scan test technique or a Built-in Self Test (BIST) have been developed as solutions for simplifying the testing of semiconductor integrated circuits. The spread of these methods has allowed the effective testing of faults that are modeled by the stuck-at fault model.
In the case of detecting faults that are modeled by the stuck-at fault model, the ability to detect faults does not depend on the clock frequency, and thus a lower clock frequency than the operating clock frequency is generally used when executing a test according to a conventional scan test technique.
However, progress in the miniaturization of semiconductor devices has also led to increased malfunction in cases where the semiconductor device is run at a high clock frequency when the semiconductor integrated circuit is actually put into use (this is shortened to “during actual operation” hereinafter). This is because the use of a high clock frequency makes variations in the product quality of the semiconductor devices after the various manufacturing processes conspicuous. Such malfunctions dependant on the clock frequency cannot be adequately tested through conventional scan test techniques with low clock frequency, however, and thus a test employing the same clock frequency as during actual operation (for example, delay testing, BIST, etc.) is necessary in order to remedy this problem.
Delay testing is in general executed using a scan test technique, in which the two operating modes of shift operation mode and normal operation mode are executed together. To detect faults that are modeled by the stuck-at fault model, a single pulse can be input in the normal operation mode when a test employing a conventional scan test technique is executed. However, two pulses must be input in the normal operation mode in a delay test, and moreover, the clock frequency of these two pulses must be the same as the clock frequency during actual operation.
Also, in order to test for defects dependant on the clock frequency when executing a BIST, a pulse at the clock frequency that is employed when the semiconductor integrated circuit including the BIST circuit is in actual use must be input to the semiconductor integrated circuit.
Conventionally, in order to meet the above described requirements, a circuit (for example, a tester) that supplies a clock signal for testing at a constant clock frequency (test clock) was separately provided outside the semiconductor integrated circuit, even when the oscillation circuit (such as a PLL) employed during actual operation was provided inside the semiconductor integrated circuit. During testing, the pulses for testing were supplied externally by switching from the input of the oscillation circuit to the input of the tester using a selector, for example.
If the input from the test clock terminal is switched to in place of the pulse from the oscillation circuit using a selector or the like in order to perform a delay test or a BIST, then a tester capable of supplying a pulse at the clock frequency during actual operation is necessary if the pulses for testing are to be supplied externally (from a tester, for example) during the test.
For example, if the clock frequency of the semiconductor integrated circuit during actual operation is 1 GHz, then a high speed tester capable of supplying a 1 GHz clock frequency for testing is necessary if a delay test or a BIST, which use the same clock frequency as during actual operation, is performed with respect to the semiconductor integrated circuit. However, a high-speed tester that is capable of supplying a 1 GHz clock frequency is extremely expensive, and would lead to an increase in costs.
A conceivable solution to this problem is to utilize the pulse that is output from the oscillation circuit inside the semiconductor integrated circuit when a high clock frequency is required during testing. The phase of the pulse that is output from the oscillation circuit cannot be found externally, however, and thus there is a risk that the pulse that is output from the oscillation circuit will assume an unstable waveform if the oscillation circuit inside the semiconductor integrated circuit is employed to execute a delay test or a BIST without altering the conventional configuration of the semiconductor integrated circuit. Hereinafter, this problem is explained in reference to the drawings.
FIG. 23 is a circuit diagram showing a conventional semiconductor integrated circuit. As shown in FIG. 23, a semiconductor integrated circuit 2000 has a clock control portion 2005, which is provided with a test clock terminal 2001, a clock switching terminal 2002, a PLL 2003, and a selector 2004, and a test circuit 2008, which is provided with flip-flops 2006 and 2007.
FIGS. 24A and 24B are diagrams that show the signal waveform of each portion of the semiconductor integrated circuit 2000 when a delay test is executed to test the test circuit 2008. The waveforms shown in FIG. 24A and 24B are the signal waveforms of the PLL 2003, the test clock terminal 2001, the clock switching terminal 2002, and the selector 2004, respectively. Here, the clock frequency of the PLL 2003 is twice the clock frequency of the test clock terminal 2001. That is, the clock frequency of the test clock terminal 2001 is half the clock frequency of the PLL 2003.
First, if the conventional semiconductor integrated circuit 2000 is tested using a default test that employs a scan test technique, then, in the shift operation mode, the output signal of the clock switching terminal 2002 is switched to 1, and a pulse from the low speed test clock terminal 2001 is supplied to the test circuit 2008 (this corresponds to the period S1 in FIGS. 24A and 24B).
Next, a switch is made to the normal operation mode (this corresponds to the point S2 in FIGS. 24A and 24B). In the normal operation mode, the clock frequency during actual operation of the semiconductor integrated circuit 2000 is required. Accordingly, the clock switching terminal 2002 is switched to 0, and a clock signal from the PLL 2003 is supplied to the test circuit 2008 (this corresponds to the period S3 in FIGS. 24A and 24B). At this time there must be exactly two pulses supplied to the test circuit 2008. Consequently, the period during which the clock switching terminal 2002 is fixed at 0 is set to the time required for two pulses from the PLL 2003.
FIG. 24A shows a case where exactly two pulses are supplied to the test circuit 2008 during the normal operation mode. However, the phase of the clock signal that is output from the PLL 2003 cannot be known from the outside, and thus there is no guarantee that the operation will always be that shown in FIG. 24A.
FIG. 24B shows a case where the phase of the clock signal of the PLL 2003 is different from that shown in FIG. 24A, and in this case the number of pulses supplied during the normal operation mode is not exactly two. In FIG. 24B, the logical value of the signal output by the PLL 2003 is 1 at the instant that the logical value of the signal output by the clock switching terminal 2002 is switched from 1 to 0. For this reason, the logical value of the signal output by the selector 2004 changes from 0 to 1, and a narrow pulse P1 is generated. As a consequence, three pulses are generated during the normal operation mode, and moreover, the operation of the circuit (more specifically, the flip-flops 2006 and 2007) cannot be guaranteed unless the pulses have at least a predetermined pulse width. Consequently, a narrow pulse P1 like that shown in FIG. 24B can become a factor that causes the test circuit 2008 to malfunction. In other words, the reliability of the test results becomes extremely low.
Next, a case in which the conventional semiconductor integrated circuit 2000 is tested using a BIST is described with reference to FIG. 25. FIG. 25 is a diagram in which a BIST circuit has been provided in place of the test circuit 2008, and shows the signal waveform of each portion of the semiconductor integrated circuit 2000 when a BIST is executed. The reference numerals in FIG. 25 denote the same components as in FIG. 24, and the clock frequencies of the PLL 2003 and test clock terminal 2001 are also the same as in FIG. 24. It should be noted that here the clock switching terminal 2002 is employed to signal the start of the BIST test.
First, the logical value of the output signal of the test clock terminal 2001 is fixed at 0, and the logical value of the output signal of the clock switching terminal 2002 is switched from 1 to 0 (this corresponds to point B1 in FIGS. 25A and 25B). Consequently, the BIST circuit starts operating.
FIG. 25A shows a case in which the pulse supplied to the BIST circuit is normal. However, as was also the case with the delay test, the phase of the clock signal that is output from the PLL 2003 cannot be known from the outside, and thus there is no guarantee that its phase will always be that shown in FIG. 25A.
FIG. 25B shows a case in which the phase of the clock signal of the PLL 2003 is different from that shown in FIG. 25A and an abnormal pulse is included in the pulses that are supplied to the BIST circuit. As shown in FIG. 25B, the logical value of the signal that is output by the PLL 2003 is 1 in the instant (B1) that the logical value of the signal output by the clock switching terminal 2002 is switched from 1 to 0. Thus, the logical value of the signal that is output from the selector 2004 is changed from 0 to 1, and a narrow pulse P2 is generated. Unless the pulses have at least a predetermined pulse width, the operation of the circuit cannot be guaranteed. Consequently, the narrow pulse P2 that is shown in FIG. 25B can become a cause of BIST circuit malfunction. That is, there is a danger that the results of a test according to a BIST technique will be incorrect.
As described above, the conventional configuration is not suited for testing with a delay test or a BIST in which the oscillation circuit inside the semiconductor integrated circuit is used.